Optimized high speed nRF24L01+ driver class documentation  1.4.2
TMRh20 2020 - Optimized fork of the nRF24L01+ driver
RF24.cpp
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1 /*
2  Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
3 
4  This program is free software; you can redistribute it and/or
5  modify it under the terms of the GNU General Public License
6  version 2 as published by the Free Software Foundation.
7  */
8 
9 #include "nRF24L01.h"
10 #include "RF24_config.h"
11 #include "RF24.h"
12 
13 
14 /****************************************************************************/
15 
16 void RF24::csn(bool mode)
17 {
18  #if defined(RF24_TINY)
19  if (ce_pin != csn_pin) {
20  digitalWrite(csn_pin, mode);
21  }
22  else {
23  if (mode == HIGH) {
24  PORTB |= (1<<PINB2); // SCK->CSN HIGH
25  delayMicroseconds(RF24_CSN_SETTLE_HIGH_DELAY); // allow csn to settle.
26  }
27  else {
28  PORTB &= ~(1<<PINB2); // SCK->CSN LOW
29  delayMicroseconds(RF24_CSN_SETTLE_LOW_DELAY); // allow csn to settle
30  }
31  }
32  // Return, CSN toggle complete
33  return;
34 
35  #elif defined (ARDUINO) && !defined(RF24_SPI_TRANSACTIONS)
36  // Minimum ideal SPI bus speed is 2x data rate
37  // If we assume 2Mbs data rate and 16Mhz clock, a
38  // divider of 4 is the minimum we want.
39  // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
40 
41  #if !defined(SOFTSPI)
42  // applies to SPI_UART and inherent hardware SPI
43  #if defined (RF24_SPI_PTR)
44  _spi->setBitOrder(MSBFIRST);
45  _spi->setDataMode(SPI_MODE0);
46 
47  #if !defined(F_CPU) || F_CPU < 20000000
48  _spi->setClockDivider(SPI_CLOCK_DIV2);
49  #elif F_CPU < 40000000
50  _spi->setClockDivider(SPI_CLOCK_DIV4);
51  #elif F_CPU < 80000000
52  _spi->setClockDivider(SPI_CLOCK_DIV8);
53  #elif F_CPU < 160000000
54  _spi->setClockDivider(SPI_CLOCK_DIV16);
55  #elif F_CPU < 320000000
56  _spi->setClockDivider(SPI_CLOCK_DIV32);
57  #elif F_CPU < 640000000
58  _spi->setClockDivider(SPI_CLOCK_DIV64);
59  #elif F_CPU < 1280000000
60  _spi->setClockDivider(SPI_CLOCK_DIV128);
61  #else // F_CPU >= 1280000000
62  #error "Unsupported CPU frequency. Please set correct SPI divider."
63  #endif // F_CPU to SPI_CLOCK_DIV translation
64 
65  #else // !defined(RF24_SPI_PTR)
66  _SPI.setBitOrder(MSBFIRST);
67  _SPI.setDataMode(SPI_MODE0);
68 
69  #if !defined(F_CPU) || F_CPU < 20000000
70  _SPI.setClockDivider(SPI_CLOCK_DIV2);
71  #elif F_CPU < 40000000
72  _SPI.setClockDivider(SPI_CLOCK_DIV4);
73  #elif F_CPU < 80000000
74  _SPI.setClockDivider(SPI_CLOCK_DIV8);
75  #elif F_CPU < 160000000
76  _SPI.setClockDivider(SPI_CLOCK_DIV16);
77  #elif F_CPU < 320000000
78  _SPI.setClockDivider(SPI_CLOCK_DIV32);
79  #elif F_CPU < 640000000
80  _SPI.setClockDivider(SPI_CLOCK_DIV64);
81  #elif F_CPU < 1280000000
82  _SPI.setClockDivider(SPI_CLOCK_DIV128);
83  #else // F_CPU >= 1280000000
84  #error "Unsupported CPU frequency. Please set correct SPI divider."
85  #endif // F_CPU to SPI_CLOCK_DIV translation
86  #endif // !defined(RF24_SPI_PTR)
87  #endif // !defined(SOFTSPI)
88 
89  #elif defined (RF24_RPi)
90  if(!mode)
91  _SPI.chipSelect(csn_pin);
92  #endif // defined(RF24_RPi)
93 
94  #if !defined(RF24_LINUX)
95  digitalWrite(csn_pin, mode);
97  #else
98  static_cast<void>(mode); // ignore -Wunused-parameter
99  #endif // !defined(RF24_LINUX)
100 }
101 
102 /****************************************************************************/
103 
104 void RF24::ce(bool level)
105 {
106  //Allow for 3-pin use on ATTiny
107  if (ce_pin != csn_pin) {
108  digitalWrite(ce_pin, level);
109  }
110 }
111 
112 /****************************************************************************/
113 
115 {
116  #if defined (RF24_SPI_TRANSACTIONS)
117  #if defined (RF24_SPI_PTR)
118  #if defined (RF24_RP2)
119  _spi->beginTransaction(spi_speed);
120  #else // ! defined (RF24_RP2)
121  _spi->beginTransaction(SPISettings(spi_speed, MSBFIRST, SPI_MODE0));
122  #endif // ! defined (RF24_RP2)
123  #else // !defined(RF24_SPI_PTR)
124  _SPI.beginTransaction(SPISettings(spi_speed, MSBFIRST, SPI_MODE0));
125  #endif // !defined(RF24_SPI_PTR)
126  #endif // defined (RF24_SPI_TRANSACTIONS)
127  csn(LOW);
128 }
129 
130 /****************************************************************************/
131 
132 inline void RF24::endTransaction()
133 {
134  csn(HIGH);
135  #if defined (RF24_SPI_TRANSACTIONS)
136  #if defined (RF24_SPI_PTR)
137  _spi->endTransaction();
138  #else // !defined(RF24_SPI_PTR)
139  _SPI.endTransaction();
140  #endif // !defined(RF24_SPI_PTR)
141  #endif // defined (RF24_SPI_TRANSACTIONS)
142 }
143 
144 /****************************************************************************/
145 
146 void RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
147 {
148  #if defined (RF24_LINUX) || defined (RF24_RP2)
149  beginTransaction(); //configures the spi settings for RPi, locks mutex and setting csn low
150  uint8_t * prx = spi_rxbuff;
151  uint8_t * ptx = spi_txbuff;
152  uint8_t size = static_cast<uint8_t>(len + 1); // Add register value to transmit buffer
153 
154  *ptx++ = (R_REGISTER | reg);
155 
156  while (len--){ *ptx++ = RF24_NOP; } // Dummy operation, just for reading
157 
158  #if defined (RF24_RP2)
159  _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, size);
160  #else // !defined (RF24_RP2)
161  _SPI.transfernb(reinterpret_cast<char *>(spi_txbuff), reinterpret_cast<char *>(spi_rxbuff), size);
162  #endif // !defined (RF24_RP2)
163 
164  status = *prx++; // status is 1st byte of receive buffer
165 
166  // decrement before to skip status byte
167  while (--size) { *buf++ = *prx++; }
168 
169  endTransaction(); // unlocks mutex and setting csn high
170 
171  #else // !defined(RF24_LINUX) && !defined(RF24_RP2)
172 
174  #if defined (RF24_SPI_PTR)
175  status = _spi->transfer(R_REGISTER | reg);
176  while (len--) { *buf++ = _spi->transfer(0xFF); }
177 
178  #else // !defined(RF24_SPI_PTR)
179  status = _SPI.transfer(R_REGISTER | reg);
180  while (len--) { *buf++ = _SPI.transfer(0xFF); }
181 
182  #endif // !defined(RF24_SPI_PTR)
183  endTransaction();
184  #endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
185 }
186 
187 /****************************************************************************/
188 
189 uint8_t RF24::read_register(uint8_t reg)
190 {
191  uint8_t result;
192 
193  #if defined (RF24_LINUX) || defined (RF24_RP2)
195 
196  uint8_t * prx = spi_rxbuff;
197  uint8_t * ptx = spi_txbuff;
198  *ptx++ = (R_REGISTER | reg);
199  *ptx++ = RF24_NOP ; // Dummy operation, just for reading
200 
201  #if defined (RF24_RP2)
202  _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, 2);
203  #else // !defined(RF24_RP2)
204  _SPI.transfernb(reinterpret_cast<char *>(spi_txbuff), reinterpret_cast<char *>(spi_rxbuff), 2);
205  #endif // !defined(RF24_RP2)
206 
207  status = *prx; // status is 1st byte of receive buffer
208  result = *++prx; // result is 2nd byte of receive buffer
209 
210  endTransaction();
211  #else // !defined(RF24_LINUX) && !defined(RF24_RP2)
212 
214  #if defined (RF24_SPI_PTR)
215  status = _spi->transfer(R_REGISTER | reg);
216  result = _spi->transfer(0xff);
217 
218  #else // !defined(RF24_SPI_PTR)
219  status = _SPI.transfer(R_REGISTER | reg);
220  result = _SPI.transfer(0xff);
221 
222  #endif // !defined(RF24_SPI_PTR)
223  endTransaction();
224  #endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
225 
226  return result;
227 }
228 
229 /****************************************************************************/
230 
231 void RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
232 {
233  #if defined (RF24_LINUX) || defined (RF24_RP2)
235  uint8_t * prx = spi_rxbuff;
236  uint8_t * ptx = spi_txbuff;
237  uint8_t size = static_cast<uint8_t>(len + 1); // Add register value to transmit buffer
238 
239  *ptx++ = (W_REGISTER | (REGISTER_MASK & reg));
240  while (len--) { *ptx++ = *buf++; }
241 
242  #if defined (RF24_RP2)
243  _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, size);
244  #else // !defined(RF24_RP2)
245  _SPI.transfernb(reinterpret_cast<char *>(spi_txbuff), reinterpret_cast<char *>(spi_rxbuff), size);
246  #endif // !defined(RF24_RP2)
247 
248  status = *prx; // status is 1st byte of receive buffer
249  endTransaction();
250  #else // !defined(RF24_LINUX) && !defined(RF24_RP2)
251 
253  #if defined (RF24_SPI_PTR)
254  status = _spi->transfer(W_REGISTER | reg);
255  while (len--) { _spi->transfer(*buf++); }
256 
257  #else // !defined(RF24_SPI_PTR)
258  status = _SPI.transfer(W_REGISTER | reg);
259  while (len--) { _SPI.transfer(*buf++); }
260 
261  #endif // !defined(RF24_SPI_PTR)
262  endTransaction();
263  #endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
264 }
265 
266 /****************************************************************************/
267 
268 void RF24::write_register(uint8_t reg, uint8_t value, bool is_cmd_only)
269 {
270  if (is_cmd_only) {
271  if (reg != RF24_NOP) { // don't print the get_status() operation
272  IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x)\r\n"), reg));
273  }
275  #if defined (RF24_LINUX)
276  status = _SPI.transfer(W_REGISTER | reg);
277  #else // !defined(RF24_LINUX) || defined (RF24_RP2)
278  #if defined (RF24_SPI_PTR)
279  status = _spi->transfer(W_REGISTER | reg);
280  #else // !defined (RF24_SPI_PTR)
281  status = _SPI.transfer(W_REGISTER | reg);
282  #endif // !defined (RF24_SPI_PTR)
283  #endif // !defined(RF24_LINUX) || defined(RF24_RP2)
284  endTransaction();
285  }
286  else {
287  IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"), reg, value));
288  #if defined (RF24_LINUX) || defined (RF24_RP2)
290  uint8_t * prx = spi_rxbuff;
291  uint8_t * ptx = spi_txbuff;
292  *ptx++ = (W_REGISTER | reg);
293  *ptx = value;
294 
295  #if defined (RF24_RP2)
296  _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, 2);
297  #else // !defined(RF24_RP2)
298  _SPI.transfernb(reinterpret_cast<char *>(spi_txbuff), reinterpret_cast<char *>(spi_rxbuff), 2);
299  #endif // !defined(RF24_RP2)
300 
301  status = *prx++; // status is 1st byte of receive buffer
302  endTransaction();
303  #else // !defined(RF24_LINUX) && !defined(RF24_RP2)
304 
306  #if defined (RF24_SPI_PTR)
307  status = _spi->transfer(W_REGISTER | reg);
308  _spi->transfer(value);
309  #else // !defined(RF24_SPI_PTR)
310  status = _SPI.transfer(W_REGISTER | reg);
311  _SPI.transfer(value);
312  #endif // !defined(RF24_SPI_PTR)
313  endTransaction();
314  #endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
315  }
316 }
317 
318 /****************************************************************************/
319 
320 void RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
321 {
322  const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
323 
324  uint8_t blank_len = !data_len ? 1 : 0;
326  data_len = rf24_min(data_len, payload_size);
327  blank_len = static_cast<uint8_t>(payload_size - data_len);
328  }
329  else {
330  data_len = rf24_min(data_len, static_cast<uint8_t>(32));
331  }
332 
333  //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
334  IF_SERIAL_DEBUG(printf("[Writing %u bytes %u blanks]\n", data_len, blank_len); );
335 
336  #if defined (RF24_LINUX) || defined (RF24_RP2)
338  uint8_t * prx = spi_rxbuff;
339  uint8_t * ptx = spi_txbuff;
340  uint8_t size;
341  size = static_cast<uint8_t>(data_len + blank_len + 1); // Add register value to transmit buffer
342 
343  *ptx++ = writeType;
344  while (data_len--) { *ptx++ = *current++; }
345  while (blank_len--) { *ptx++ = 0; }
346 
347  #if defined (RF24_RP2)
348  _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, size);
349  #else // !defined(RF24_RP2)
350  _SPI.transfernb(reinterpret_cast<char *>(spi_txbuff), reinterpret_cast<char *>(spi_rxbuff), size);
351  #endif // !defined(RF24_RP2)
352 
353  status = *prx; // status is 1st byte of receive buffer
354  endTransaction();
355 
356  #else // !defined(RF24_LINUX) && !defined(RF24_RP2)
357 
359  #if defined (RF24_SPI_PTR)
360  status = _spi->transfer(writeType);
361  while (data_len--) { _spi->transfer(*current++); }
362  while (blank_len--) { _spi->transfer(0); }
363 
364  #else // !defined(RF24_SPI_PTR)
365  status = _SPI.transfer(writeType);
366  while (data_len--) { _SPI.transfer(*current++); }
367 
368  while (blank_len--) { _SPI.transfer(0); }
369 
370  #endif // !defined(RF24_SPI_PTR)
371  endTransaction();
372  #endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
373 }
374 
375 /****************************************************************************/
376 
377 void RF24::read_payload(void* buf, uint8_t data_len)
378 {
379  uint8_t* current = reinterpret_cast<uint8_t*>(buf);
380 
381  uint8_t blank_len = 0;
383  data_len = rf24_min(data_len, payload_size);
384  blank_len = static_cast<uint8_t>(payload_size - data_len);
385  }
386  else {
387  data_len = rf24_min(data_len, static_cast<uint8_t>(32));
388  }
389 
390  //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
391 
392  IF_SERIAL_DEBUG(printf("[Reading %u bytes %u blanks]\n", data_len, blank_len); );
393 
394  #if defined (RF24_LINUX) || defined (RF24_RP2)
396  uint8_t * prx = spi_rxbuff;
397  uint8_t * ptx = spi_txbuff;
398  uint8_t size;
399  size = static_cast<uint8_t>(data_len + blank_len + 1); // Add register value to transmit buffer
400 
401  *ptx++ = R_RX_PAYLOAD;
402  while(--size) { *ptx++ = RF24_NOP; }
403 
404  size = static_cast<uint8_t>(data_len + blank_len + 1); // Size has been lost during while, re affect
405 
406  #if defined (RF24_RP2)
407  _spi->transfernb((const uint8_t*)spi_txbuff, spi_rxbuff, size);
408  #else // !defined(RF24_RP2)
409  _SPI.transfernb(reinterpret_cast<char *>(spi_txbuff), reinterpret_cast<char *>(spi_rxbuff), size);
410  #endif // !defined(RF24_RP2)
411 
412  status = *prx++; // 1st byte is status
413 
414  if (data_len > 0) {
415  // Decrement before to skip 1st status byte
416  while (--data_len) { *current++ = *prx++; }
417 
418  *current = *prx;
419  }
420  endTransaction();
421  #else // !defined(RF24_LINUX) && !defined(RF24_RP2)
422 
424  #if defined (RF24_SPI_PTR)
425  status = _spi->transfer(R_RX_PAYLOAD);
426  while (data_len--) { *current++ = _spi->transfer(0xFF); }
427 
428  while (blank_len--) { _spi->transfer(0xFF); }
429 
430  #else // !defined(RF24_SPI_PTR)
431  status = _SPI.transfer(R_RX_PAYLOAD);
432  while (data_len--) { *current++ = _SPI.transfer(0xFF); }
433  while (blank_len--) { _SPI.transfer(0xff); }
434 
435  #endif // !defined(RF24_SPI_PTR)
436  endTransaction();
437 
438  #endif // !defined(RF24_LINUX) && !defined(RF24_RP2)
439 }
440 
441 /****************************************************************************/
442 
443 uint8_t RF24::flush_rx(void)
444 {
445  write_register(FLUSH_RX, RF24_NOP, true);
446  return status;
447 }
448 
449 /****************************************************************************/
450 
451 uint8_t RF24::flush_tx(void)
452 {
453  write_register(FLUSH_TX, RF24_NOP, true);
454  return status;
455 }
456 
457 /****************************************************************************/
458 
459 uint8_t RF24::get_status(void)
460 {
461  write_register(RF24_NOP, RF24_NOP, true);
462  return status;
463 }
464 
465 /****************************************************************************/
466 #if !defined(MINIMAL)
467 
468 void RF24::print_status(uint8_t _status)
469 {
470  printf_P(PSTR("STATUS\t\t= 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"), _status, (_status & _BV(RX_DR)) ? 1 : 0,
471  (_status & _BV(TX_DS)) ? 1 : 0, (_status & _BV(MAX_RT)) ? 1 : 0, ((_status >> RX_P_NO) & 0x07), (_status & _BV(TX_FULL)) ? 1 : 0);
472 }
473 
474 /****************************************************************************/
475 
476 
477 void RF24::print_observe_tx(uint8_t value)
478 {
479  printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"), value, (value >> PLOS_CNT) & 0x0F, (value >> ARC_CNT) & 0x0F);
480 }
481 
482 /****************************************************************************/
483 
484 void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
485 {
486  //char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
487  //printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
488  #if defined(RF24_LINUX)
489  printf("%s\t=", name);
490  #else // !defined(RF24_LINUX)
491  printf_P(PSTR(PRIPSTR"\t="),name);
492  #endif // !defined(RF24_LINUX)
493  while (qty--) {
494  printf_P(PSTR(" 0x%02x"), read_register(reg++));
495  }
496  printf_P(PSTR("\r\n"));
497 }
498 
499 /****************************************************************************/
500 
501 void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
502 {
503 
504  #if defined(RF24_LINUX)
505  printf("%s\t=", name);
506  #else // !defined(RF24_LINUX)
507  printf_P(PSTR(PRIPSTR"\t="), name);
508  #endif // !defined(RF24_LINUX)
509  uint8_t *buffer = new uint8_t[addr_width];
510  while (qty--) {
511  read_register(reg++ & REGISTER_MASK, buffer, addr_width);
512 
513  printf_P(PSTR(" 0x"));
514  uint8_t* bufptr = buffer + addr_width;
515  while (--bufptr >= buffer) {
516  printf_P(PSTR("%02x"), *bufptr);
517  }
518  }
519  delete[] buffer;
520  printf_P(PSTR("\r\n"));
521 }
522 
523 #endif // !defined(MINIMAL)
524 
525 /****************************************************************************/
526 
527 RF24::RF24(uint16_t _cepin, uint16_t _cspin, uint32_t _spi_speed)
528  :ce_pin(_cepin), csn_pin(_cspin), spi_speed(_spi_speed), payload_size(32), _is_p_variant(false), _is_p0_rx(false), addr_width(5), dynamic_payloads_enabled(true),
529  csDelay(5)
530 {
531  _init_obj();
532 }
533 
534 /****************************************************************************/
535 
536 RF24::RF24(uint32_t _spi_speed)
537  :ce_pin(0xFFFF), csn_pin(0xFFFF), spi_speed(_spi_speed), payload_size(32), _is_p_variant(false), _is_p0_rx(false), addr_width(5), dynamic_payloads_enabled(true),
538  csDelay(5)
539 {
540  _init_obj();
541 }
542 
543 /****************************************************************************/
544 
545 void RF24::_init_obj()
546 {
547  // Use a pointer on the Arduino platform
548 
549  #if defined (RF24_SPI_PTR) && !defined (RF24_RP2)
550  _spi = &SPI;
551  #endif // defined (RF24_SPI_PTR)
552 
553  pipe0_reading_address[0] = 0;
554  if(spi_speed <= 35000){ //Handle old BCM2835 speed constants, default to RF24_SPI_SPEED
555  spi_speed = RF24_SPI_SPEED;
556  }
557 }
558 
559 /****************************************************************************/
560 
561 void RF24::setChannel(uint8_t channel)
562 {
563  const uint8_t max_channel = 125;
564  write_register(RF_CH, rf24_min(channel, max_channel));
565 }
566 
568 {
569  return read_register(RF_CH);
570 }
571 
572 /****************************************************************************/
573 
574 void RF24::setPayloadSize(uint8_t size)
575 {
576  // payload size must be in range [1, 32]
577  payload_size = static_cast<uint8_t>(rf24_max(1, rf24_min(32, size)));
578 
579  // write static payload size setting for all pipes
580  for (uint8_t i = 0; i < 6; ++i)
581  write_register(static_cast<uint8_t>(RX_PW_P0 + i), payload_size);
582 }
583 
584 /****************************************************************************/
585 
586 uint8_t RF24::getPayloadSize(void)
587 {
588  return payload_size;
589 }
590 
591 /****************************************************************************/
592 
593 #if !defined(MINIMAL)
594 
595 static const PROGMEM char rf24_datarate_e_str_0[] = "= 1 MBPS";
596 static const PROGMEM char rf24_datarate_e_str_1[] = "= 2 MBPS";
597 static const PROGMEM char rf24_datarate_e_str_2[] = "= 250 KBPS";
598 static const PROGMEM char * const rf24_datarate_e_str_P[] = {
602 };
603 static const PROGMEM char rf24_model_e_str_0[] = "nRF24L01";
604 static const PROGMEM char rf24_model_e_str_1[] = "nRF24L01+";
605 static const PROGMEM char * const rf24_model_e_str_P[] = {
608 };
609 static const PROGMEM char rf24_crclength_e_str_0[] = "= Disabled";
610 static const PROGMEM char rf24_crclength_e_str_1[] = "= 8 bits";
611 static const PROGMEM char rf24_crclength_e_str_2[] = "= 16 bits" ;
612 static const PROGMEM char * const rf24_crclength_e_str_P[] = {
616 };
617 static const PROGMEM char rf24_pa_dbm_e_str_0[] = "= PA_MIN";
618 static const PROGMEM char rf24_pa_dbm_e_str_1[] = "= PA_LOW";
619 static const PROGMEM char rf24_pa_dbm_e_str_2[] = "= PA_HIGH";
620 static const PROGMEM char rf24_pa_dbm_e_str_3[] = "= PA_MAX";
621 static const PROGMEM char * const rf24_pa_dbm_e_str_P[] = {
626 };
627 
628  #if defined(RF24_LINUX)
629 static const char rf24_csn_e_str_0[] = "CE0 (PI Hardware Driven)";
630 static const char rf24_csn_e_str_1[] = "CE1 (PI Hardware Driven)";
631 static const char rf24_csn_e_str_2[] = "CE2 (PI Hardware Driven)";
632 static const char rf24_csn_e_str_3[] = "Custom GPIO Software Driven";
633 static const char * const rf24_csn_e_str_P[] = {
634  rf24_csn_e_str_0,
635  rf24_csn_e_str_1,
636  rf24_csn_e_str_2,
637  rf24_csn_e_str_3,
638 };
639  #endif // defined(RF24_LINUX)
640 
641 static const PROGMEM char rf24_feature_e_str_on[] = "= Enabled";
642 static const PROGMEM char rf24_feature_e_str_allowed[] = "= Allowed";
643 static const PROGMEM char rf24_feature_e_str_open[] = " open ";
644 static const PROGMEM char rf24_feature_e_str_closed[] = "closed";
645 static const PROGMEM char * const rf24_feature_e_str_P[] = {
651 };
652 
654 {
655 
656  #if defined(RF24_LINUX)
657  printf("================ SPI Configuration ================\n" );
658  uint8_t bus_ce = static_cast<uint8_t>(csn_pin % 10);
659  uint8_t bus_numb = static_cast<uint8_t>((csn_pin - bus_ce) / 10);
660  printf("CSN Pin\t\t= /dev/spidev%d.%d\n", bus_numb, bus_ce);
661  printf("CE Pin\t\t= Custom GPIO%d\n", ce_pin);
662  #endif
663  printf_P(PSTR("SPI Speedz\t= %d Mhz\n"), static_cast<uint8_t>(spi_speed / 1000000)); //Print the SPI speed on non-Linux devices
664  #if defined(RF24_LINUX)
665  printf("================ NRF Configuration ================\n");
666  #endif // defined(RF24_LINUX)
667 
668  print_status(get_status());
669 
670  print_address_register(PSTR("RX_ADDR_P0-1"), RX_ADDR_P0, 2);
671  print_byte_register(PSTR("RX_ADDR_P2-5"), RX_ADDR_P2, 4);
672  print_address_register(PSTR("TX_ADDR\t"), TX_ADDR);
673 
674  print_byte_register(PSTR("RX_PW_P0-6"), RX_PW_P0, 6);
675  print_byte_register(PSTR("EN_AA\t"), EN_AA);
676  print_byte_register(PSTR("EN_RXADDR"), EN_RXADDR);
677  print_byte_register(PSTR("RF_CH\t"), RF_CH);
678  print_byte_register(PSTR("RF_SETUP"), RF_SETUP);
679  print_byte_register(PSTR("CONFIG\t"), NRF_CONFIG);
680  print_byte_register(PSTR("DYNPD/FEATURE"), DYNPD, 2);
681 
682  printf_P(PSTR("Data Rate\t"
683  PRIPSTR
684  "\r\n"), (char *)(pgm_read_ptr(&rf24_datarate_e_str_P[getDataRate()])));
685  printf_P(PSTR("Model\t\t= "
686  PRIPSTR
687  "\r\n"), (char *)(pgm_read_ptr(&rf24_model_e_str_P[isPVariant()])));
688  printf_P(PSTR("CRC Length\t"
689  PRIPSTR
690  "\r\n"), (char *)(pgm_read_ptr(&rf24_crclength_e_str_P[getCRCLength()])));
691  printf_P(PSTR("PA Power\t"
692  PRIPSTR
693  "\r\n"), (char *)(pgm_read_ptr(&rf24_pa_dbm_e_str_P[getPALevel()])));
694  printf_P(PSTR("ARC\t\t= %d\r\n"), getARC());
695 }
696 
698 
699  #if defined(RF24_LINUX)
700  printf("================ SPI Configuration ================\n");
701  uint8_t bus_ce = static_cast<uint8_t>(csn_pin % 10);
702  uint8_t bus_numb = static_cast<uint8_t>((csn_pin - bus_ce) / 10);
703  printf("CSN Pin\t\t\t= /dev/spidev%d.%d\n", bus_numb, bus_ce);
704  printf("CE Pin\t\t\t= Custom GPIO%d\n", ce_pin);
705  #endif
706  printf_P(PSTR("SPI Frequency\t\t= %d Mhz\n"), static_cast<uint8_t>(spi_speed / 1000000)); //Print the SPI speed on non-Linux devices
707  #if defined(RF24_LINUX)
708  printf("================ NRF Configuration ================\n");
709  #endif // defined(RF24_LINUX)
710 
711  uint8_t channel = getChannel();
712  uint16_t frequency = static_cast<uint16_t>(channel + 2400);
713  printf_P(PSTR("Channel\t\t\t= %u (~ %u MHz)\r\n"), channel, frequency);
714 
715  printf_P(PSTR("RF Data Rate\t\t"
716  PRIPSTR
717  "\r\n"), (char *)(pgm_read_ptr(&rf24_datarate_e_str_P[getDataRate()])));
718  printf_P(PSTR("RF Power Amplifier\t"
719  PRIPSTR
720  "\r\n"), (char *)(pgm_read_ptr(&rf24_pa_dbm_e_str_P[getPALevel()])));
721  printf_P(PSTR("RF Low Noise Amplifier\t"
722  PRIPSTR
723  "\r\n"), (char *)(pgm_read_ptr(&rf24_feature_e_str_P[(read_register(RF_SETUP) & 1) * 1])));
724  printf_P(PSTR("CRC Length\t\t"
725  PRIPSTR
726  "\r\n"), (char *)(pgm_read_ptr(&rf24_crclength_e_str_P[getCRCLength()])));
727  printf_P(PSTR("Address Length\t\t= %d bytes\r\n"), (read_register(SETUP_AW) & 3) + 2);
728  printf_P(PSTR("Static Payload Length\t= %d bytes\r\n"), getPayloadSize());
729 
730  uint8_t setupRetry = read_register(SETUP_RETR);
731  printf_P(PSTR("Auto Retry Delay\t= %d microseconds\r\n"), (setupRetry >> ARD) * 250 + 250);
732  printf_P(PSTR("Auto Retry Attempts\t= %d maximum\r\n"), setupRetry & 0x0F);
733 
734  uint8_t observeTx = read_register(OBSERVE_TX);
735  printf_P(PSTR("Packets lost on\n current channel\t= %d\r\n"), observeTx >> 4);
736  printf_P(PSTR("Retry attempts made for\n last transmission\t= %d\r\n"), observeTx & 0x0F);
737 
738  uint8_t features = read_register(FEATURE);
739  printf_P(PSTR("Multicast\t\t"
740  PRIPSTR
741  "\r\n"), (char *)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<bool>(features & _BV(EN_DYN_ACK)) * 2])));
742  printf_P(PSTR("Custom ACK Payload\t"
743  PRIPSTR
744  "\r\n"), (char *)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<bool>(features & _BV(EN_ACK_PAY)) * 1])));
745 
746  uint8_t dynPl = read_register(DYNPD);
747  printf_P(PSTR("Dynamic Payloads\t"
748  PRIPSTR
749  "\r\n"), (char *)(pgm_read_ptr(&rf24_feature_e_str_P[(dynPl && (features &_BV(EN_DPL))) * 1])));
750 
751  uint8_t autoAck = read_register(EN_AA);
752  if (autoAck == 0x3F || autoAck == 0) {
753  // all pipes have the same configuration about auto-ack feature
754  printf_P(PSTR("Auto Acknowledgment\t"
755  PRIPSTR
756  "\r\n"), (char *)(pgm_read_ptr(&rf24_feature_e_str_P[static_cast<bool>(autoAck) * 1])));
757  } else {
758  // representation per pipe
759  printf_P(PSTR("Auto Acknowledgment\t= 0b%c%c%c%c%c%c\r\n"),
760  static_cast<char>(static_cast<bool>(autoAck & _BV(ENAA_P5)) + 48),
761  static_cast<char>(static_cast<bool>(autoAck & _BV(ENAA_P4)) + 48),
762  static_cast<char>(static_cast<bool>(autoAck & _BV(ENAA_P3)) + 48),
763  static_cast<char>(static_cast<bool>(autoAck & _BV(ENAA_P2)) + 48),
764  static_cast<char>(static_cast<bool>(autoAck & _BV(ENAA_P1)) + 48),
765  static_cast<char>(static_cast<bool>(autoAck & _BV(ENAA_P0)) + 48));
766  }
767 
768  config_reg = read_register(NRF_CONFIG);
769  printf_P(PSTR("Primary Mode\t\t= %cX\r\n"), config_reg & _BV(PRIM_RX) ? 'R' : 'T');
770  print_address_register(PSTR("TX address\t"), TX_ADDR);
771 
772  uint8_t openPipes = read_register(EN_RXADDR);
773  for (uint8_t i = 0; i < 6; ++i) {
774  bool isOpen = openPipes & _BV(i);
775  printf_P(PSTR("pipe %u ("
776  PRIPSTR
777  ") bound"), i, (char *)(pgm_read_ptr(&rf24_feature_e_str_P[isOpen + 3])));
778  if (i < 2) {
779  print_address_register(PSTR(""), static_cast<uint8_t>(RX_ADDR_P0 + i));
780  }
781  else {
782  print_byte_register(PSTR(""), static_cast<uint8_t>(RX_ADDR_P0 + i));
783  }
784  }
785 }
786 #endif // !defined(MINIMAL)
787 
788 /****************************************************************************/
789 #if defined (RF24_SPI_PTR) || defined (DOXYGEN_FORCED)
790 // does not apply to RF24_LINUX
791 
792 bool RF24::begin(_SPI* spiBus)
793 {
794  _spi = spiBus;
795  return _init_pins() && _init_radio();
796 }
797 
798 /****************************************************************************/
799 
800 bool RF24::begin(_SPI* spiBus, uint16_t _cepin, uint16_t _cspin)
801 {
802  ce_pin = _cepin;
803  csn_pin = _cspin;
804  return begin(spiBus);
805 }
806 
807 #endif // defined (RF24_SPI_PTR) || defined (DOXYGEN_FORCED)
808 
809 /****************************************************************************/
810 
811 bool RF24::begin(uint16_t _cepin, uint16_t _cspin)
812 {
813  ce_pin = _cepin;
814  csn_pin = _cspin;
815  return begin();
816 }
817 
818 /****************************************************************************/
819 
820 bool RF24::begin(void)
821 {
822  #if defined (RF24_LINUX)
823  #if defined (RF24_RPi)
824  switch(csn_pin) { // Ensure valid hardware CS pin
825  case 0: break;
826  case 1: break;
827  // Allow BCM2835 enums for RPi
828  case 8: csn_pin = 0; break;
829  case 7: csn_pin = 1; break;
830  case 18: csn_pin = 10; break; // to make it work on SPI1
831  case 17: csn_pin = 11; break;
832  case 16: csn_pin = 12; break;
833  default: csn_pin = 0; break;
834  }
835  #endif // RF24_RPi
836 
837  _SPI.begin(csn_pin, spi_speed);
838 
839  #elif defined (XMEGA_D3)
840  _spi->begin(csn_pin);
841 
842  #elif defined (RF24_RP2)
843  _spi->begin(PICO_DEFAULT_SPI ? spi1 : spi0);
844 
845  #else // using an Arduino platform || defined (LITTLEWIRE)
846 
847  #if defined (RF24_SPI_PTR)
848  _spi->begin();
849  #else // !defined(RF24_SPI_PTR)
850  _SPI.begin();
851  #endif // !defined(RF24_SPI_PTR)
852 
853  #endif // !defined(XMEGA_D3) && !defined(RF24_LINUX)
854 
855  return _init_pins() && _init_radio();
856 }
857 
858 /****************************************************************************/
859 
860 bool RF24::_init_pins()
861 {
862  if (!isValid()) {
863  // didn't specify the CSN & CE pins to c'tor nor begin()
864  return false;
865  }
866 
867  #if defined (RF24_LINUX)
868 
869  #if defined (MRAA)
870  GPIO();
871  gpio.begin(ce_pin, csn_pin);
872  #endif
873 
874  pinMode(ce_pin, OUTPUT);
875  ce(LOW);
876  delay(100);
877 
878  #elif defined (LITTLEWIRE)
879  pinMode(csn_pin, OUTPUT);
880  csn(HIGH);
881 
882  #elif defined (XMEGA_D3)
883  if (ce_pin != csn_pin) {
884  pinMode(ce_pin, OUTPUT);
885  };
886  ce(LOW);
887  csn(HIGH);
888  delay(200);
889 
890  #else // using an Arduino platform
891 
892  // Initialize pins
893  if (ce_pin != csn_pin) {
894  pinMode(ce_pin, OUTPUT);
895  pinMode(csn_pin, OUTPUT);
896  }
897 
898  ce(LOW);
899  csn(HIGH);
900 
901  #if defined (__ARDUINO_X86__)
902  delay(100);
903  #endif
904  #endif // !defined(XMEGA_D3) && !defined(LITTLEWIRE) && !defined(RF24_LINUX)
905 
906  return true; // assuming pins are connected properly
907 }
908 
909 /****************************************************************************/
910 
911 bool RF24::_init_radio()
912 {
913  // Must allow the radio time to settle else configuration bits will not necessarily stick.
914  // This is actually only required following power up but some settling time also appears to
915  // be required after resets too. For full coverage, we'll always assume the worst.
916  // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
917  // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
918  // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
919  delay(5);
920 
921  // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
922  // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
923  // sizes must never be used. See datasheet for a more complete explanation.
924  setRetries(5, 15);
925 
926  // Then set the data rate to the slowest (and most reliable) speed supported by all
927  // hardware. Since this value occupies the same register as the PA level value, set
928  // the PA level to MAX
929  setRadiation(RF24_PA_MAX, RF24_1MBPS); // LNA enabled by default
930 
931  // detect if is a plus variant & use old toggle features command accordingly
932  uint8_t before_toggle = read_register(FEATURE);
933  toggle_features();
934  uint8_t after_toggle = read_register(FEATURE);
935  _is_p_variant = before_toggle == after_toggle;
936  if (after_toggle){
937  if (_is_p_variant){
938  // module did not experience power-on-reset (#401)
939  toggle_features();
940  }
941  // allow use of multicast parameter and dynamic payloads by default
942  write_register(FEATURE, 0);
943  }
944  ack_payloads_enabled = false; // ack payloads disabled by default
945  write_register(DYNPD, 0); // disable dynamic payloads by default (for all pipes)
946  dynamic_payloads_enabled = false;
947  write_register(EN_AA, 0x3F); // enable auto-ack on all pipes
948  write_register(EN_RXADDR, 3); // only open RX pipes 0 & 1
949  setPayloadSize(32); // set static payload size to 32 (max) bytes by default
950  setAddressWidth(5); // set default address length to (max) 5 bytes
951 
952  // Set up default configuration. Callers can always change it later.
953  // This channel should be universally safe and not bleed over into adjacent
954  // spectrum.
955  setChannel(76);
956 
957  // Reset current status
958  // Notice reset and flush is the last thing we do
959  write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT));
960 
961 
962  // Flush buffers
963  flush_rx();
964  flush_tx();
965 
966  // Clear CONFIG register:
967  // Reflect all IRQ events on IRQ pin
968  // Enable PTX
969  // Power Up
970  // 16-bit CRC (CRC required by auto-ack)
971  // Do not write CE high so radio will remain in standby I mode
972  // PTX should use only 22uA of power
973  write_register(NRF_CONFIG, (_BV(EN_CRC) | _BV(CRCO)) );
974  config_reg = read_register(NRF_CONFIG);
975 
976  powerUp();
977 
978  // if config is not set correctly then there was a bad response from module
979  return config_reg == (_BV(EN_CRC) | _BV(CRCO) | _BV(PWR_UP)) ? true : false;
980 }
981 
982 /****************************************************************************/
983 
985 {
986  return read_register(SETUP_AW) == (addr_width - static_cast<uint8_t>(2));
987 }
988 
989 /****************************************************************************/
990 
992 {
993  return ce_pin != 0xFFFF && csn_pin != 0xFFFF;
994 }
995 
996 /****************************************************************************/
997 
999 {
1000  #if !defined(RF24_TINY) && !defined(LITTLEWIRE)
1001  powerUp();
1002  #endif
1003  config_reg |= _BV(PRIM_RX);
1004  write_register(NRF_CONFIG, config_reg);
1005  write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT));
1006  ce(HIGH);
1007 
1008  // Restore the pipe0 address, if exists
1009  if (_is_p0_rx) {
1010  write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
1011  } else {
1012  closeReadingPipe(0);
1013  }
1014 }
1015 
1016 /****************************************************************************/
1017 static const PROGMEM uint8_t child_pipe_enable[] = {ERX_P0, ERX_P1, ERX_P2,
1018  ERX_P3, ERX_P4, ERX_P5};
1019 
1021 {
1022  ce(LOW);
1023 
1024  //delayMicroseconds(100);
1025  delayMicroseconds(static_cast<int>(txDelay));
1026  if (ack_payloads_enabled){
1027  flush_tx();
1028  }
1029 
1030  config_reg = static_cast<uint8_t>(config_reg & ~_BV(PRIM_RX));
1031  write_register(NRF_CONFIG, config_reg);
1032 
1033  #if defined(RF24_TINY) || defined(LITTLEWIRE)
1034  // for 3 pins solution TX mode is only left with additonal powerDown/powerUp cycle
1035  if (ce_pin == csn_pin) {
1036  powerDown();
1037  powerUp();
1038  }
1039  #endif
1040  write_register(EN_RXADDR, static_cast<uint8_t>(read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0])))); // Enable RX on pipe0
1041 }
1042 
1043 /****************************************************************************/
1044 
1046 {
1047  ce(LOW); // Guarantee CE is low on powerDown
1048  config_reg = static_cast<uint8_t>(config_reg & ~_BV(PWR_UP));
1049  write_register(NRF_CONFIG, config_reg);
1050 }
1051 
1052 /****************************************************************************/
1053 
1054 //Power up now. Radio will not power down unless instructed by MCU for config changes etc.
1055 void RF24::powerUp(void)
1056 {
1057  // if not powered up then power up and wait for the radio to initialize
1058  if (!(config_reg & _BV(PWR_UP))) {
1059  config_reg |= _BV(PWR_UP);
1060  write_register(NRF_CONFIG, config_reg);
1061 
1062  // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
1063  // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
1064  // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
1066  }
1067 }
1068 
1069 /******************************************************************/
1070 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
1071 
1072 void RF24::errNotify()
1073 {
1074  #if defined (SERIAL_DEBUG) || defined (RF24_LINUX)
1075  printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
1076  #endif
1077  #if defined (FAILURE_HANDLING)
1078  failureDetected = 1;
1079  #else
1080  delay(5000);
1081  #endif
1082 }
1083 
1084 #endif
1085 /******************************************************************/
1086 
1087 //Similar to the previous write, clears the interrupt flags
1088 bool RF24::write(const void* buf, uint8_t len, const bool multicast)
1089 {
1090  //Start Writing
1091  startFastWrite(buf, len, multicast);
1092 
1093  //Wait until complete or failed
1094  #if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1095  uint32_t timer = millis();
1096  #endif // defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1097 
1098  while (!(get_status() & (_BV(TX_DS) | _BV(MAX_RT)))) {
1099  #if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1100  if (millis() - timer > 95) {
1101  errNotify();
1102  #if defined(FAILURE_HANDLING)
1103  return 0;
1104  #else
1105  delay(100);
1106  #endif
1107  }
1108  #endif
1109  }
1110 
1111  ce(LOW);
1112 
1113  write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT));
1114 
1115  //Max retries exceeded
1116  if (status & _BV(MAX_RT)) {
1117  flush_tx(); // Only going to be 1 packet in the FIFO at a time using this method, so just flush
1118  return 0;
1119  }
1120  //TX OK 1 or 0
1121  return 1;
1122 }
1123 
1124 bool RF24::write(const void* buf, uint8_t len)
1125 {
1126  return write(buf, len, 0);
1127 }
1128 /****************************************************************************/
1129 
1130 //For general use, the interrupt flags are not important to clear
1131 bool RF24::writeBlocking(const void* buf, uint8_t len, uint32_t timeout)
1132 {
1133  //Block until the FIFO is NOT full.
1134  //Keep track of the MAX retries and set auto-retry if seeing failures
1135  //This way the FIFO will fill up and allow blocking until packets go through
1136  //The radio will auto-clear everything in the FIFO as long as CE remains high
1137 
1138  uint32_t timer = millis(); // Get the time that the payload transmission started
1139 
1140  while ((get_status() & (_BV(TX_FULL)))) { // Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
1141 
1142  if (status & _BV(MAX_RT)) { // If MAX Retries have been reached
1143  reUseTX(); // Set re-transmit and clear the MAX_RT interrupt flag
1144  if (millis() - timer > timeout) {
1145  return 0; // If this payload has exceeded the user-defined timeout, exit and return 0
1146  }
1147  }
1148  #if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1149  if (millis() - timer > (timeout + 95)) {
1150  errNotify();
1151  #if defined(FAILURE_HANDLING)
1152  return 0;
1153  #endif
1154  }
1155  #endif
1156 
1157  }
1158 
1159  //Start Writing
1160  startFastWrite(buf, len, 0); // Write the payload if a buffer is clear
1161 
1162  return 1; // Return 1 to indicate successful transmission
1163 }
1164 
1165 /****************************************************************************/
1166 
1168 {
1169  write_register(NRF_STATUS, _BV(MAX_RT)); //Clear max retry flag
1170  write_register(REUSE_TX_PL, RF24_NOP, true);
1171  ce(LOW); //Re-Transfer packet
1172  ce(HIGH);
1173 }
1174 
1175 /****************************************************************************/
1176 
1177 bool RF24::writeFast(const void* buf, uint8_t len, const bool multicast)
1178 {
1179  //Block until the FIFO is NOT full.
1180  //Keep track of the MAX retries and set auto-retry if seeing failures
1181  //Return 0 so the user can control the retrys and set a timer or failure counter if required
1182  //The radio will auto-clear everything in the FIFO as long as CE remains high
1183 
1184  #if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1185  uint32_t timer = millis();
1186  #endif
1187 
1188  //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
1189  while ((get_status() & (_BV(TX_FULL)))) {
1190  if (status & _BV(MAX_RT)) {
1191  return 0; //Return 0. The previous payload has not been retransmitted
1192  // From the user perspective, if you get a 0, just keep trying to send the same payload
1193  }
1194  #if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1195  if (millis() - timer > 95) {
1196  errNotify();
1197  #if defined(FAILURE_HANDLING)
1198  return 0;
1199  #endif // defined(FAILURE_HANDLING)
1200  }
1201  #endif
1202  }
1203  startFastWrite(buf, len, multicast); // Start Writing
1204 
1205  return 1;
1206 }
1207 
1208 bool RF24::writeFast(const void* buf, uint8_t len)
1209 {
1210  return writeFast(buf, len, 0);
1211 }
1212 
1213 /****************************************************************************/
1214 
1215 //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
1216 //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
1217 //Otherwise we enter Standby-II mode, which is still faster than standby mode
1218 //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
1219 
1220 void RF24::startFastWrite(const void* buf, uint8_t len, const bool multicast, bool startTx)
1221 { //TMRh20
1222 
1223  write_payload(buf, len, multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD);
1224  if (startTx) {
1225  ce(HIGH);
1226  }
1227 }
1228 
1229 /****************************************************************************/
1230 
1231 //Added the original startWrite back in so users can still use interrupts, ack payloads, etc
1232 //Allows the library to pass all tests
1233 bool RF24::startWrite(const void* buf, uint8_t len, const bool multicast)
1234 {
1235 
1236  // Send the payload
1237  write_payload(buf, len, multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD);
1238  ce(HIGH);
1239  #if !defined(F_CPU) || F_CPU > 20000000
1240  delayMicroseconds(10);
1241  #endif
1242  ce(LOW);
1243  return !(status & _BV(TX_FULL));
1244 }
1245 
1246 /****************************************************************************/
1247 
1249 {
1250  return read_register(FIFO_STATUS) & _BV(RX_FULL);
1251 }
1252 
1253 /****************************************************************************/
1254 
1256 {
1257 
1258  #if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1259  uint32_t timeout = millis();
1260  #endif
1261  while (!(read_register(FIFO_STATUS) & _BV(TX_EMPTY))) {
1262  if (status & _BV(MAX_RT)) {
1263  write_register(NRF_STATUS, _BV(MAX_RT));
1264  ce(LOW);
1265  flush_tx(); //Non blocking, flush the data
1266  return 0;
1267  }
1268  #if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1269  if (millis() - timeout > 95) {
1270  errNotify();
1271  #if defined(FAILURE_HANDLING)
1272  return 0;
1273  #endif
1274  }
1275  #endif
1276  }
1277 
1278  ce(LOW); //Set STANDBY-I mode
1279  return 1;
1280 }
1281 
1282 /****************************************************************************/
1283 
1284 bool RF24::txStandBy(uint32_t timeout, bool startTx)
1285 {
1286 
1287  if (startTx) {
1288  stopListening();
1289  ce(HIGH);
1290  }
1291  uint32_t start = millis();
1292 
1293  while (!(read_register(FIFO_STATUS) & _BV(TX_EMPTY))) {
1294  if (status & _BV(MAX_RT)) {
1295  write_register(NRF_STATUS, _BV(MAX_RT));
1296  ce(LOW); // Set re-transmit
1297  ce(HIGH);
1298  if (millis() - start >= timeout) {
1299  ce(LOW);
1300  flush_tx();
1301  return 0;
1302  }
1303  }
1304  #if defined(FAILURE_HANDLING) || defined(RF24_LINUX)
1305  if (millis() - start > (timeout + 95)) {
1306  errNotify();
1307  #if defined(FAILURE_HANDLING)
1308  return 0;
1309  #endif
1310  }
1311  #endif
1312  }
1313 
1314  ce(LOW); //Set STANDBY-I mode
1315  return 1;
1316 
1317 }
1318 
1319 /****************************************************************************/
1320 
1321 void RF24::maskIRQ(bool tx, bool fail, bool rx)
1322 {
1323  /* clear the interrupt flags */
1324  config_reg = static_cast<uint8_t>(config_reg & ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR));
1325  /* set the specified interrupt flags */
1326  config_reg = static_cast<uint8_t>(config_reg | fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR);
1327  write_register(NRF_CONFIG, config_reg);
1328 }
1329 
1330 /****************************************************************************/
1331 
1333 {
1334  uint8_t result = read_register(R_RX_PL_WID);
1335 
1336  if (result > 32) {
1337  flush_rx();
1338  delay(2);
1339  return 0;
1340  }
1341  return result;
1342 }
1343 
1344 /****************************************************************************/
1345 
1347 {
1348  return available(NULL);
1349 }
1350 
1351 /****************************************************************************/
1352 
1353 bool RF24::available(uint8_t* pipe_num)
1354 {
1355  // get implied RX FIFO empty flag from status byte
1356  uint8_t pipe = (get_status() >> RX_P_NO) & 0x07;
1357  if (pipe > 5)
1358  return 0;
1359 
1360  // If the caller wants the pipe number, include that
1361  if (pipe_num)
1362  *pipe_num = pipe;
1363 
1364  return 1;
1365 }
1366 
1367 /****************************************************************************/
1368 
1369 void RF24::read(void* buf, uint8_t len)
1370 {
1371 
1372  // Fetch the payload
1373  read_payload(buf, len);
1374 
1375  //Clear the only applicable interrupt flags
1376  write_register(NRF_STATUS, _BV(RX_DR));
1377 
1378 }
1379 
1380 /****************************************************************************/
1381 
1382 void RF24::whatHappened(bool& tx_ok, bool& tx_fail, bool& rx_ready)
1383 {
1384  // Read the status & reset the status in one easy call
1385  // Or is that such a good idea?
1386  write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT));
1387 
1388  // Report to the user what happened
1389  tx_ok = status & _BV(TX_DS);
1390  tx_fail = status & _BV(MAX_RT);
1391  rx_ready = status & _BV(RX_DR);
1392 }
1393 
1394 /****************************************************************************/
1395 
1396 void RF24::openWritingPipe(uint64_t value)
1397 {
1398  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
1399  // expects it LSB first too, so we're good.
1400 
1401  write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
1402  write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
1403 }
1404 
1405 /****************************************************************************/
1406 void RF24::openWritingPipe(const uint8_t* address)
1407 {
1408  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
1409  // expects it LSB first too, so we're good.
1410  write_register(RX_ADDR_P0, address, addr_width);
1411  write_register(TX_ADDR, address, addr_width);
1412 }
1413 
1414 /****************************************************************************/
1415 static const PROGMEM uint8_t child_pipe[] = {RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2,
1417 
1418 void RF24::openReadingPipe(uint8_t child, uint64_t address)
1419 {
1420  // If this is pipe 0, cache the address. This is needed because
1421  // openWritingPipe() will overwrite the pipe 0 address, so
1422  // startListening() will have to restore it.
1423  if (child == 0) {
1424  memcpy(pipe0_reading_address, &address, addr_width);
1425  _is_p0_rx = true;
1426  }
1427 
1428  if (child <= 5) {
1429  // For pipes 2-5, only write the LSB
1430  if (child < 2) {
1431  write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
1432  } else {
1433  write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
1434  }
1435 
1436  // Note it would be more efficient to set all of the bits for all open
1437  // pipes at once. However, I thought it would make the calling code
1438  // more simple to do it this way.
1439  write_register(EN_RXADDR, static_cast<uint8_t>(read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))));
1440  }
1441 }
1442 
1443 /****************************************************************************/
1444 
1445 void RF24::setAddressWidth(uint8_t a_width)
1446 {
1447  a_width = static_cast<uint8_t>(a_width - 2);
1448  if (a_width) {
1449  write_register(SETUP_AW, static_cast<uint8_t>(a_width % 4));
1450  addr_width = static_cast<uint8_t>((a_width % 4) + 2);
1451  } else {
1452  write_register(SETUP_AW, static_cast<uint8_t>(0));
1453  addr_width = static_cast<uint8_t>(2);
1454  }
1455 
1456 }
1457 
1458 /****************************************************************************/
1459 
1460 void RF24::openReadingPipe(uint8_t child, const uint8_t* address)
1461 {
1462  // If this is pipe 0, cache the address. This is needed because
1463  // openWritingPipe() will overwrite the pipe 0 address, so
1464  // startListening() will have to restore it.
1465  if (child == 0) {
1466  memcpy(pipe0_reading_address, address, addr_width);
1467  _is_p0_rx = true;
1468  }
1469  if (child <= 5) {
1470  // For pipes 2-5, only write the LSB
1471  if (child < 2) {
1472  write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
1473  } else {
1474  write_register(pgm_read_byte(&child_pipe[child]), address, 1);
1475  }
1476 
1477  // Note it would be more efficient to set all of the bits for all open
1478  // pipes at once. However, I thought it would make the calling code
1479  // more simple to do it this way.
1480  write_register(EN_RXADDR, static_cast<uint8_t>(read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))));
1481 
1482  }
1483 }
1484 
1485 /****************************************************************************/
1486 
1487 void RF24::closeReadingPipe(uint8_t pipe)
1488 {
1489  write_register(EN_RXADDR, static_cast<uint8_t>(read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe]))));
1490  if (!pipe) {
1491  // keep track of pipe 0's RX state to avoid null vs 0 in addr cache
1492  _is_p0_rx = false;
1493  }
1494 }
1495 
1496 /****************************************************************************/
1497 
1498 void RF24::toggle_features(void)
1499 {
1500  beginTransaction();
1501  #if defined (RF24_SPI_PTR)
1502  status = _spi->transfer(ACTIVATE);
1503  _spi->transfer(0x73);
1504  #else
1505  status = _SPI.transfer(ACTIVATE);
1506  _SPI.transfer(0x73);
1507  #endif
1508  endTransaction();
1509 }
1510 
1511 /****************************************************************************/
1512 
1514 {
1515  // Enable dynamic payload throughout the system
1516 
1517  //toggle_features();
1518  write_register(FEATURE, read_register(FEATURE) | _BV(EN_DPL));
1519 
1520  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n", read_register(FEATURE)));
1521 
1522  // Enable dynamic payload on all pipes
1523  //
1524  // Not sure the use case of only having dynamic payload on certain
1525  // pipes, so the library does not support it.
1526  write_register(DYNPD, read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
1527 
1528  dynamic_payloads_enabled = true;
1529 }
1530 
1531 /****************************************************************************/
1533 {
1534  // Disables dynamic payload throughout the system. Also disables Ack Payloads
1535 
1536  //toggle_features();
1537  write_register(FEATURE, 0);
1538 
1539  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n", read_register(FEATURE)));
1540 
1541  // Disable dynamic payload on all pipes
1542  //
1543  // Not sure the use case of only having dynamic payload on certain
1544  // pipes, so the library does not support it.
1545  write_register(DYNPD, 0);
1546 
1547  dynamic_payloads_enabled = false;
1548  ack_payloads_enabled = false;
1549 }
1550 
1551 /****************************************************************************/
1552 
1554 {
1555  // enable ack payloads and dynamic payload features
1556 
1557  if (!ack_payloads_enabled){
1558  write_register(FEATURE, read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL));
1559 
1560  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n", read_register(FEATURE)));
1561 
1562  // Enable dynamic payload on pipes 0 & 1
1563  write_register(DYNPD, read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
1564  dynamic_payloads_enabled = true;
1565  ack_payloads_enabled = true;
1566  }
1567 }
1568 
1569 /****************************************************************************/
1570 
1572 {
1573  // disable ack payloads (leave dynamic payload features as is)
1574  if (ack_payloads_enabled){
1575  write_register(FEATURE, static_cast<uint8_t>(read_register(FEATURE) | ~_BV(EN_ACK_PAY)));
1576 
1577  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n", read_register(FEATURE)));
1578 
1579  ack_payloads_enabled = false;
1580  }
1581 }
1582 
1583 /****************************************************************************/
1584 
1586 {
1587  //
1588  // enable dynamic ack features
1589  //
1590  //toggle_features();
1591  write_register(FEATURE, read_register(FEATURE) | _BV(EN_DYN_ACK));
1592 
1593  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n", read_register(FEATURE)));
1594 }
1595 
1596 /****************************************************************************/
1597 
1598 bool RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
1599 {
1600  if (ack_payloads_enabled){
1601  const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
1602 
1603  write_payload(current, len, W_ACK_PAYLOAD | (pipe & 0x07));
1604  return !(status & _BV(TX_FULL));
1605  }
1606  return 0;
1607 }
1608 
1609 /****************************************************************************/
1610 
1612 {
1613  return available(NULL);
1614 }
1615 
1616 /****************************************************************************/
1617 
1619 {
1620  return _is_p_variant;
1621 }
1622 
1623 /****************************************************************************/
1624 
1625 void RF24::setAutoAck(bool enable)
1626 {
1627  if (enable){
1628  write_register(EN_AA, 0x3F);
1629  }else{
1630  write_register(EN_AA, 0);
1631  // accomodate ACK payloads feature
1632  if (ack_payloads_enabled){
1634  }
1635  }
1636 }
1637 
1638 /****************************************************************************/
1639 
1640 void RF24::setAutoAck(uint8_t pipe, bool enable)
1641 {
1642  if (pipe < 6) {
1643  uint8_t en_aa = read_register(EN_AA);
1644  if (enable) {
1645  en_aa |= static_cast<uint8_t>(_BV(pipe));
1646  }else{
1647  en_aa = static_cast<uint8_t>(en_aa & ~_BV(pipe));
1648  if (ack_payloads_enabled && !pipe){
1650  }
1651  }
1652  write_register(EN_AA, en_aa);
1653  }
1654 }
1655 
1656 /****************************************************************************/
1657 
1659 {
1660  return (read_register(CD) & 1);
1661 }
1662 
1663 /****************************************************************************/
1664 
1665 bool RF24::testRPD(void)
1666 {
1667  return (read_register(RPD) & 1);
1668 }
1669 
1670 /****************************************************************************/
1671 
1672 void RF24::setPALevel(uint8_t level, bool lnaEnable)
1673 {
1674  uint8_t setup = read_register(RF_SETUP) & static_cast<uint8_t>(0xF8);
1675  setup |= _pa_level_reg_value(level, lnaEnable);
1676  write_register(RF_SETUP, setup);
1677 }
1678 
1679 /****************************************************************************/
1680 
1681 uint8_t RF24::getPALevel(void)
1682 {
1683 
1684  return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1;
1685 }
1686 
1687 /****************************************************************************/
1688 
1689 uint8_t RF24::getARC(void)
1690 {
1691 
1692  return read_register(OBSERVE_TX) & 0x0F;
1693 }
1694 
1695 /****************************************************************************/
1696 
1698 {
1699  bool result = false;
1700  uint8_t setup = read_register(RF_SETUP);
1701 
1702  // HIGH and LOW '00' is 1Mbs - our default
1703  setup = static_cast<uint8_t>(setup & ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)));
1704  setup |= _data_rate_reg_value(speed);
1705 
1706  write_register(RF_SETUP, setup);
1707 
1708  // Verify our result
1709  if (read_register(RF_SETUP) == setup) {
1710  result = true;
1711  }
1712  return result;
1713 }
1714 
1715 /****************************************************************************/
1716 
1718 {
1719  rf24_datarate_e result;
1720  uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
1721 
1722  // switch uses RAM (evil!)
1723  // Order matters in our case below
1724  if (dr == _BV(RF_DR_LOW)) {
1725  // '10' = 250KBPS
1726  result = RF24_250KBPS;
1727  } else if (dr == _BV(RF_DR_HIGH)) {
1728  // '01' = 2MBPS
1729  result = RF24_2MBPS;
1730  } else {
1731  // '00' = 1MBPS
1732  result = RF24_1MBPS;
1733  }
1734  return result;
1735 }
1736 
1737 /****************************************************************************/
1738 
1740 {
1741  config_reg = static_cast<uint8_t>(config_reg & ~(_BV(CRCO) | _BV(EN_CRC)));
1742 
1743  // switch uses RAM (evil!)
1744  if (length == RF24_CRC_DISABLED) {
1745  // Do nothing, we turned it off above.
1746  } else if (length == RF24_CRC_8) {
1747  config_reg |= _BV(EN_CRC);
1748  } else {
1749  config_reg |= _BV(EN_CRC);
1750  config_reg |= _BV(CRCO);
1751  }
1752  write_register(NRF_CONFIG, config_reg);
1753 }
1754 
1755 /****************************************************************************/
1756 
1758 {
1760  uint8_t AA = read_register(EN_AA);
1761  config_reg = read_register(NRF_CONFIG);
1762 
1763  if (config_reg & _BV(EN_CRC) || AA) {
1764  if (config_reg & _BV(CRCO)) {
1765  result = RF24_CRC_16;
1766  } else {
1767  result = RF24_CRC_8;
1768  }
1769  }
1770 
1771  return result;
1772 }
1773 
1774 /****************************************************************************/
1775 
1777 {
1778  config_reg = static_cast<uint8_t>(config_reg & ~_BV(EN_CRC));
1779  write_register(NRF_CONFIG, config_reg);
1780 }
1781 
1782 /****************************************************************************/
1783 void RF24::setRetries(uint8_t delay, uint8_t count)
1784 {
1785  write_register(SETUP_RETR, static_cast<uint8_t>(rf24_min(15, delay) << ARD | rf24_min(15, count)));
1786 }
1787 
1788 /****************************************************************************/
1789 void RF24::startConstCarrier(rf24_pa_dbm_e level, uint8_t channel)
1790 {
1791  stopListening();
1792  write_register(RF_SETUP, read_register(RF_SETUP) | _BV(CONT_WAVE) | _BV(PLL_LOCK));
1793  if (isPVariant()){
1794  setAutoAck(0);
1795  setRetries(0, 0);
1796  uint8_t dummy_buf[32];
1797  for (uint8_t i = 0; i < 32; ++i)
1798  dummy_buf[i] = 0xFF;
1799 
1800  // use write_register() instead of openWritingPipe() to bypass
1801  // truncation of the address with the current RF24::addr_width value
1802  write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&dummy_buf), 5);
1803  flush_tx(); // so we can write to top level
1804 
1805  // use write_register() instead of write_payload() to bypass
1806  // truncation of the payload with the current RF24::payload_size value
1807  write_register(W_TX_PAYLOAD, reinterpret_cast<const uint8_t*>(&dummy_buf), 32);
1808 
1809  disableCRC();
1810  }
1811  setPALevel(level);
1812  setChannel(channel);
1813  IF_SERIAL_DEBUG(printf_P(PSTR("RF_SETUP=%02x\r\n"), read_register(RF_SETUP)));
1814  ce(HIGH);
1815  if (isPVariant()){
1816  delay(1); // datasheet says 1 ms is ok in this instance
1817  ce(LOW);
1818  reUseTX();
1819  }
1820 }
1821 
1822 /****************************************************************************/
1823 
1825 {
1826  /*
1827  * A note from the datasheet:
1828  * Do not use REUSE_TX_PL together with CONT_WAVE=1. When both these
1829  * registers are set the chip does not react when setting CE low. If
1830  * however, both registers are set PWR_UP = 0 will turn TX mode off.
1831  */
1832  powerDown(); // per datasheet recommendation (just to be safe)
1833  write_register(RF_SETUP, static_cast<uint8_t>(read_register(RF_SETUP) & ~_BV(CONT_WAVE) & ~_BV(PLL_LOCK)));
1834  ce(LOW);
1835 }
1836 
1837 /****************************************************************************/
1838 
1839 void RF24::toggleAllPipes(bool isEnabled)
1840 {
1841  write_register(EN_RXADDR, static_cast<uint8_t>(isEnabled ? 0x3F : 0));
1842 }
1843 
1844 /****************************************************************************/
1845 
1846 uint8_t RF24::_data_rate_reg_value(rf24_datarate_e speed)
1847 {
1848  #if !defined(F_CPU) || F_CPU > 20000000
1849  txDelay = 280;
1850  #else //16Mhz Arduino
1851  txDelay=85;
1852  #endif
1853  if (speed == RF24_250KBPS) {
1854  #if !defined(F_CPU) || F_CPU > 20000000
1855  txDelay = 505;
1856  #else //16Mhz Arduino
1857  txDelay = 155;
1858  #endif
1859  // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
1860  // Making it '10'.
1861  return static_cast<uint8_t>(_BV(RF_DR_LOW));
1862  }
1863  else if (speed == RF24_2MBPS) {
1864  #if !defined(F_CPU) || F_CPU > 20000000
1865  txDelay = 240;
1866  #else // 16Mhz Arduino
1867  txDelay = 65;
1868  #endif
1869  // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
1870  // Making it '01'
1871  return static_cast<uint8_t>(_BV(RF_DR_HIGH));
1872  }
1873  // HIGH and LOW '00' is 1Mbs - our default
1874  return static_cast<uint8_t>(0);
1875 
1876 }
1877 
1878 /****************************************************************************/
1879 
1880 uint8_t RF24::_pa_level_reg_value(uint8_t level, bool lnaEnable)
1881 {
1882  // If invalid level, go to max PA
1883  // Else set level as requested
1884  // + lnaEnable (1 or 0) to support the SI24R1 chip extra bit
1885  return static_cast<uint8_t>(((level > RF24_PA_MAX ? static_cast<uint8_t>(RF24_PA_MAX) : level) << 1) + lnaEnable);
1886 }
1887 
1888 /****************************************************************************/
1889 
1890 void RF24::setRadiation(uint8_t level, rf24_datarate_e speed, bool lnaEnable)
1891 {
1892  uint8_t setup = _data_rate_reg_value(speed);
1893  setup |= _pa_level_reg_value(level, lnaEnable);
1894  write_register(RF_SETUP, setup);
1895 }
static const PROGMEM char rf24_datarate_e_str_1[]
Definition: RF24.cpp:596
static const PROGMEM char rf24_feature_e_str_on[]
Definition: RF24.cpp:641
static const PROGMEM char rf24_feature_e_str_open[]
Definition: RF24.cpp:643
static const PROGMEM char rf24_feature_e_str_closed[]
Definition: RF24.cpp:644
static const PROGMEM char *const rf24_datarate_e_str_P[]
Definition: RF24.cpp:598
static const PROGMEM char rf24_pa_dbm_e_str_2[]
Definition: RF24.cpp:619
static const PROGMEM char rf24_model_e_str_0[]
Definition: RF24.cpp:603
static const PROGMEM char rf24_pa_dbm_e_str_0[]
Definition: RF24.cpp:617
static const PROGMEM char *const rf24_crclength_e_str_P[]
Definition: RF24.cpp:612
static const PROGMEM char *const rf24_feature_e_str_P[]
Definition: RF24.cpp:645
static const PROGMEM char rf24_datarate_e_str_0[]
Definition: RF24.cpp:595
static const PROGMEM char rf24_crclength_e_str_2[]
Definition: RF24.cpp:611
static const PROGMEM char *const rf24_pa_dbm_e_str_P[]
Definition: RF24.cpp:621
static const PROGMEM char rf24_feature_e_str_allowed[]
Definition: RF24.cpp:642
static const PROGMEM uint8_t child_pipe[]
Definition: RF24.cpp:1415
static const PROGMEM char rf24_model_e_str_1[]
Definition: RF24.cpp:604
static const PROGMEM uint8_t child_pipe_enable[]
Definition: RF24.cpp:1017
static const PROGMEM char rf24_crclength_e_str_1[]
Definition: RF24.cpp:610
static const PROGMEM char rf24_crclength_e_str_0[]
Definition: RF24.cpp:609
static const PROGMEM char *const rf24_model_e_str_P[]
Definition: RF24.cpp:605
static const PROGMEM char rf24_datarate_e_str_2[]
Definition: RF24.cpp:597
static const PROGMEM char rf24_pa_dbm_e_str_1[]
Definition: RF24.cpp:618
static const PROGMEM char rf24_pa_dbm_e_str_3[]
Definition: RF24.cpp:620
#define RF24_POWERUP_DELAY
Definition: RF24_config.h:35
#define RF24_SPI_SPEED
The default SPI speed (in Hz)
Definition: RF24_config.h:44
#define rf24_min(a, b)
Definition: RF24_config.h:40
#define rf24_max(a, b)
Definition: RF24_config.h:39
void disableAckPayload(void)
Definition: RF24.cpp:1571
bool begin(void)
Definition: RF24.cpp:820
uint8_t getPayloadSize(void)
Definition: RF24.cpp:586
RF24(uint16_t _cepin, uint16_t _cspin, uint32_t _spi_speed=RF24_SPI_SPEED)
Definition: RF24.cpp:527
bool available(void)
Definition: RF24.cpp:1346
bool txStandBy()
Definition: RF24.cpp:1255
void endTransaction()
Definition: RF24.cpp:132
bool failureDetected
Definition: RF24.h:1193
void startListening(void)
Definition: RF24.cpp:998
bool isAckPayloadAvailable(void)
Definition: RF24.cpp:1611
void printPrettyDetails(void)
Definition: RF24.cpp:697
void setPayloadSize(uint8_t size)
Definition: RF24.cpp:574
bool isValid()
Definition: RF24.cpp:991
bool writeAckPayload(uint8_t pipe, const void *buf, uint8_t len)
Definition: RF24.cpp:1598
void stopConstCarrier(void)
Definition: RF24.cpp:1824
bool dynamic_payloads_enabled
Definition: RF24.h:159
void enableDynamicPayloads(void)
Definition: RF24.cpp:1513
bool writeFast(const void *buf, uint8_t len)
Definition: RF24.cpp:1208
void disableDynamicPayloads(void)
Definition: RF24.cpp:1532
void setRetries(uint8_t delay, uint8_t count)
Definition: RF24.cpp:1783
bool write(const void *buf, uint8_t len)
Definition: RF24.cpp:1124
uint8_t getARC(void)
Definition: RF24.cpp:1689
uint8_t flush_rx(void)
Definition: RF24.cpp:443
void beginTransaction()
Definition: RF24.cpp:114
void powerUp(void)
Definition: RF24.cpp:1055
void setChannel(uint8_t channel)
Definition: RF24.cpp:561
void disableCRC(void)
Definition: RF24.cpp:1776
void enableDynamicAck()
Definition: RF24.cpp:1585
bool isPVariant(void)
Definition: RF24.cpp:1618
uint8_t getDynamicPayloadSize(void)
Definition: RF24.cpp:1332
bool ack_payloads_enabled
Definition: RF24.h:157
uint8_t getChannel(void)
Definition: RF24.cpp:567
void stopListening(void)
Definition: RF24.cpp:1020
rf24_datarate_e getDataRate(void)
Definition: RF24.cpp:1717
bool testRPD(void)
Definition: RF24.cpp:1665
void setCRCLength(rf24_crclength_e length)
Definition: RF24.cpp:1739
void read(void *buf, uint8_t len)
Definition: RF24.cpp:1369
uint32_t txDelay
Definition: RF24.h:1600
void closeReadingPipe(uint8_t pipe)
Definition: RF24.cpp:1487
void read_register(uint8_t reg, uint8_t *buf, uint8_t len)
Definition: RF24.cpp:146
void openReadingPipe(uint8_t number, const uint8_t *address)
Definition: RF24.cpp:1460
void powerDown(void)
Definition: RF24.cpp:1045
void toggleAllPipes(bool isEnabled)
Open or close all data pipes.
Definition: RF24.cpp:1839
uint8_t addr_width
Definition: RF24.h:158
void setPALevel(uint8_t level, bool lnaEnable=1)
Definition: RF24.cpp:1672
rf24_crclength_e getCRCLength(void)
Definition: RF24.cpp:1757
void maskIRQ(bool tx_ok, bool tx_fail, bool rx_ready)
Definition: RF24.cpp:1321
void enableAckPayload(void)
Definition: RF24.cpp:1553
bool isChipConnected()
Definition: RF24.cpp:984
void startConstCarrier(rf24_pa_dbm_e level, uint8_t channel)
Definition: RF24.cpp:1789
void startFastWrite(const void *buf, uint8_t len, const bool multicast, bool startTx=1)
Definition: RF24.cpp:1220
uint32_t csDelay
Definition: RF24.h:1610
bool testCarrier(void)
Definition: RF24.cpp:1658
bool rxFifoFull()
Definition: RF24.cpp:1248
void setAddressWidth(uint8_t a_width)
Definition: RF24.cpp:1445
void setRadiation(uint8_t level, rf24_datarate_e speed, bool lnaEnable=true)
configure the RF_SETUP register in 1 transaction
Definition: RF24.cpp:1890
uint8_t flush_tx(void)
Definition: RF24.cpp:451
bool startWrite(const void *buf, uint8_t len, const bool multicast)
Definition: RF24.cpp:1233
void printDetails(void)
Definition: RF24.cpp:653
bool writeBlocking(const void *buf, uint8_t len, uint32_t timeout)
Definition: RF24.cpp:1131
void reUseTX()
Definition: RF24.cpp:1167
bool setDataRate(rf24_datarate_e speed)
Definition: RF24.cpp:1697
void setAutoAck(bool enable)
Definition: RF24.cpp:1625
void openWritingPipe(const uint8_t *address)
Definition: RF24.cpp:1406
uint8_t getPALevel(void)
Definition: RF24.cpp:1681
void whatHappened(bool &tx_ok, bool &tx_fail, bool &rx_ready)
Definition: RF24.cpp:1382
rf24_crclength_e
Definition: RF24.h:100
@ RF24_CRC_16
Definition: RF24.h:106
@ RF24_CRC_DISABLED
Definition: RF24.h:102
@ RF24_CRC_8
Definition: RF24.h:104
rf24_datarate_e
Definition: RF24.h:80
@ RF24_2MBPS
Definition: RF24.h:84
@ RF24_250KBPS
Definition: RF24.h:86
@ RF24_1MBPS
Definition: RF24.h:82
rf24_pa_dbm_e
Definition: RF24.h:36
@ RF24_PA_MAX
Definition: RF24.h:64
GPIO()
#define pinMode(pin, direction)
#define _BV(x)
#define HIGH
#define OUTPUT
#define delay(milisec)
#define printf_P
#define PROGMEM
#define PRIPSTR
#define delayMicroseconds(usec)
#define PSTR(x)
#define _SPI
#define IF_SERIAL_DEBUG(x)
#define LOW
#define digitalWrite(pin, value)
#define millis()
#define pgm_read_byte(p)
#define RX_ADDR_P3
Definition: nRF24L01.h:40
#define RX_PW_P0
Definition: nRF24L01.h:44
#define PRIM_RX
Definition: nRF24L01.h:61
#define CD
Definition: nRF24L01.h:36
#define ERX_P2
Definition: nRF24L01.h:71
#define MASK_MAX_RT
Definition: nRF24L01.h:57
#define R_RX_PL_WID
Definition: nRF24L01.h:108
#define CONT_WAVE
Definition: nRF24L01.h:78
#define EN_ACK_PAY
Definition: nRF24L01.h:100
#define EN_DPL
Definition: nRF24L01.h:99
#define SETUP_RETR
Definition: nRF24L01.h:31
#define CRCO
Definition: nRF24L01.h:59
#define ERX_P0
Definition: nRF24L01.h:73
#define ERX_P4
Definition: nRF24L01.h:69
#define RF_PWR_HIGH
Definition: nRF24L01.h:128
#define EN_DYN_ACK
Definition: nRF24L01.h:101
#define ENAA_P0
Definition: nRF24L01.h:67
#define REUSE_TX_PL
Definition: nRF24L01.h:114
#define RX_DR
Definition: nRF24L01.h:81
#define ENAA_P4
Definition: nRF24L01.h:63
#define W_REGISTER
Definition: nRF24L01.h:105
#define DPL_P2
Definition: nRF24L01.h:96
#define R_RX_PAYLOAD
Definition: nRF24L01.h:109
#define OBSERVE_TX
Definition: nRF24L01.h:35
#define RF24_NOP
Definition: nRF24L01.h:115
#define RX_ADDR_P5
Definition: nRF24L01.h:42
#define ERX_P3
Definition: nRF24L01.h:70
#define RF_CH
Definition: nRF24L01.h:32
#define MASK_RX_DR
Definition: nRF24L01.h:55
#define NRF_STATUS
Definition: nRF24L01.h:34
#define ERX_P1
Definition: nRF24L01.h:72
#define W_TX_PAYLOAD_NO_ACK
Definition: nRF24L01.h:122
#define RX_FULL
Definition: nRF24L01.h:91
#define DPL_P4
Definition: nRF24L01.h:94
#define W_ACK_PAYLOAD
Definition: nRF24L01.h:111
#define REGISTER_MASK
Definition: nRF24L01.h:106
#define DPL_P5
Definition: nRF24L01.h:93
#define ENAA_P2
Definition: nRF24L01.h:65
#define FIFO_STATUS
Definition: nRF24L01.h:50
#define RF_PWR_LOW
Definition: nRF24L01.h:127
#define TX_ADDR
Definition: nRF24L01.h:43
#define EN_AA
Definition: nRF24L01.h:28
#define ARD
Definition: nRF24L01.h:75
#define ARC_CNT
Definition: nRF24L01.h:87
#define RX_P_NO
Definition: nRF24L01.h:84
#define ENAA_P3
Definition: nRF24L01.h:64
#define DPL_P1
Definition: nRF24L01.h:97
#define FLUSH_RX
Definition: nRF24L01.h:113
#define NRF_CONFIG
Definition: nRF24L01.h:27
#define MAX_RT
Definition: nRF24L01.h:83
#define TX_DS
Definition: nRF24L01.h:82
#define EN_RXADDR
Definition: nRF24L01.h:29
#define RPD
Definition: nRF24L01.h:121
#define FLUSH_TX
Definition: nRF24L01.h:112
#define RF_DR_LOW
Definition: nRF24L01.h:125
#define RX_ADDR_P2
Definition: nRF24L01.h:39
#define RF_DR_HIGH
Definition: nRF24L01.h:126
#define DPL_P0
Definition: nRF24L01.h:98
#define ACTIVATE
Definition: nRF24L01.h:107
#define RX_ADDR_P1
Definition: nRF24L01.h:38
#define MASK_TX_DS
Definition: nRF24L01.h:56
#define DPL_P3
Definition: nRF24L01.h:95
#define RF_SETUP
Definition: nRF24L01.h:33
#define RX_ADDR_P0
Definition: nRF24L01.h:37
#define FEATURE
Definition: nRF24L01.h:52
#define ENAA_P1
Definition: nRF24L01.h:66
#define ENAA_P5
Definition: nRF24L01.h:62
#define TX_EMPTY
Definition: nRF24L01.h:90
#define DYNPD
Definition: nRF24L01.h:51
#define EN_CRC
Definition: nRF24L01.h:58
#define PWR_UP
Definition: nRF24L01.h:60
#define TX_FULL
Definition: nRF24L01.h:85
#define PLOS_CNT
Definition: nRF24L01.h:86
#define SETUP_AW
Definition: nRF24L01.h:30
#define PLL_LOCK
Definition: nRF24L01.h:77
#define ERX_P5
Definition: nRF24L01.h:68
#define R_REGISTER
Definition: nRF24L01.h:104
#define RX_ADDR_P4
Definition: nRF24L01.h:41
#define W_TX_PAYLOAD
Definition: nRF24L01.h:110